Memory ordering in CPUs

I frequently see statements about differences between strongly ordered architectures (like x86 or SPARC) and weakly ordered architectures (like ARM or RISC-V), with the confident assertion that weakly ordered machines are inherently much more scalable than strongly ordered ones. The key misconception is the implicit assumption that CPUs of all stripes actually obey their memory model for every memory access. They, emphatically, do not. They promise to behave as if they did. There’s a world of difference in that seemingly minor distinction. To be clear, some CPU cores actually obey the architectural memory ordering rules to the letter. But this kind of behavior is usually limited to tiny cores or microcontrollers, frequently without a cache. Basically everything else (and that includes bigger in-order designs!) cuts some corners. Specifically, they normally implement memory ordering optimistically. It is assumed that most loads access data that hasn’t been modified by another core…