Hot Chips 2026: Samsung and HBM Base Die Opportunities

HBM, or High Bandwidth Memory, stacks multiple DRAM dies on top of a base die. The dies interface with each other via TSVs, while the base die talks with whatever compute die is using the memory via an interposer. Increasing bandwidth for a new HBM generation involves scaling up bandwidth between the DRAM dies and the base die, as well as scaling bandwidth from the base die to the host. Denser TSVs and more TSVs can easily achieve the former. The latter is more challenging, because the physical interface between the base die and host is already the biggest consumer of base die area. Increasing data pin count makes the area problem worse, and is bad for power consumption. Samsung notes that even though each HBM generation improves power efficiency, memory power keeps going up.Samsung answered this challenge by switching to a logic node, moving away from fabricating the base die on a DRAM node. HBM4 and HBM4E now use their 4nm logic process. A logic node helps mitigate power draw…