RISCV memory access

This is a small summary of why accessing memory when debugging a riscv cpu is complicated.It is work in progress, the current code is available on swindle's github.IntroductionAs usual, as it is RISCV, a lot is optional with important details left to implementationSo let's see what is possible (definition from Gemini):Recommended : Program Buffer Execution (ProgBuf): Memory is accessed by halting the CPU and executing standard load or store instructions placed into a dedicated buffer. This uses the core's native pipeline, meaning all MMU translations, Physical Memory Protection (PMP), and cache hierarchy rules apply automatically.Optional: System Bus Access (SysBus): The Debug Module acts as an independent master directly on the system interconnect, bypassing the CPU entirely. This allows reading or writing physical memory while the core is actively running, though it does not go through the CPU's MMU or local L1/L2 caches. (NB this is more or less what ARM does).Optional : Access…