How do bitwidths actually work in Verilog?

This post introduces a project that Gabriel Desfrene did in my group as an intern last summer. Gabriel will present his project in a paper coauthored with my PhD students Quentin Corradi and Michalis Pardalos and myself at CAV 2026 in July. Verilog (aka SystemVerilog) is the most widely used language for specifying, designing, and verifying all kinds of computer hardware. But some aspects of the language are widely misunderstood – even some as fundamental as “how many bits are used for each operation”. Consider this example, which is due to Quentin: logic [3:0] foo; assign foo = (3'b110 + 3'b110 + 3'b110 + 3'b110) >> 2; The first line is declaring foo to be 4-bit variable. On the second line, 3'b110 is Verilog for “the 3-bit binary number 110”, and >> is the right-shift operation. That is, we are performing the addition of four copies of 110, then shifting to the right by 2, and finally storing the result in foo. Verilog is a hardware description language: it describes pieces of…