The need for new instructions: atomic bit fill and drain

In the previous article, I proposed a new lockless channel architecture based on two bit vectors. One is used to reserve access to a memory region, the other to commit changes. I showed promising theoretical performance improvements: whereas existing architectures pay the cost of linearizability without clients being able to take advantage of such consistency, lockless bags allow each element in the channel to be operated upon fully independently. In theory. In practice, hardware processes atomic operations by locking cache lines. Readers and writers in lockless bags need to modify both bit vectors, which means locking both cache lines and neutering any performance benefits offered by lockless bags. How can we fix this? Hardware needs to give software an efficient mechanism for locking memory regions. New instructions: atomic_bit_{fill,drain} and atomic_bit_set Here are the proposed signatures: atomic_bit_{fill,drain}: {cache line address, max # bits} => {changed bit mask}…